1. Field of the Invention
This invention relates to electronic digital data processing systems incorporating a special instruction processor such as a floating point accelerator processor. More specifically, the invention relates to a new and improved interconnection arrangement between a floating point processor and a central processor unit.
2. Description of the Prior Art
A digital data processing system comprises three elements: namely, a memory element, an input/output element, and a processor element. The memory element stores information in addressable storage locations, with each location having a unique address. The information stored in the memory includes data, or "operands", and instructions for processing the operands. The processor element transfers information to and from the memory element, interprets the information as either instructions or operands and processes the operands in accordance with the associated instructions. The input/output element, under control of the processor unit, also communicates with the memory element in order to transfer operands and instructions into the system and obtain processed data from it.
Operands processed by a processing unit may take a number of forms. In many processing operations, operands are in the form of integers or whole numbers. In other operations, operands are in a floating point format, that is, in what is typically known as "scientific notation". In this form, an operand has two parts, including an exponent and a mantissa. In a binary-based system used in most computers, the mantissa is a fraction with a binary point to the immediate left of the most significant digit, and the exponent represents the power of two to which the mantissa must be taken to obtain the value of the number. Each of the mantissa and the exponent may contain a sign, either positive or negative.
Similarly, operands for trigonometric functions may have a different form from both integer and floating point operands. For instance, some trigonometric functions may be repetitive for each multiple of three hundred and sixty degrees, if the operands are expressed in degrees, or may represent or require specific operations with respect to "pi" if the operands are expressed in radian notation. In addition to the scientific notation or special trigonometric function, other special operand notations are conceivable.
Each of these special classes of operands may require special handling by the processor. With respect particularly to floating point instructions, a number of arrangements for processing such operands have been attempted in the prior art. In some data processing systems, the central processing unit contains special control circuitry for executing the special instructions. Even with this hardware approach, floating point instructions usually require significantly more time to complete than do instructions on conventional integer operands. As a central processor unit executes all instructions, including the floating point instructions in seriatum, the execution of floating point instructions by the central processor can significantly increase the overall time to complete a given program.
In another approach, the operands are processed using subroutines comprising sets of the machine instructions to implement the floating point functions. The central processor unit merely uses a floating point instruction as an instruction directing the processor to execute the appropriate subroutine. This approach enables the functions performed by the special class of instructions to be altered relatively simply. However, this approach is considerably slower than the hardware approach, as the mantissas and exponents of the operands must be handled separately.
In other prior data processing systems, separate functional modules operating in parallel execute the instructions of the data processing system. In some cases, each module can execute all of the instructions on the different classes of operands, or specific modules may be assigned to process instructions on selected classes of operands. In either case, each module operates independently by retrieving data from or storing data in the memory unit directly. A controlling module may retrieve the instructions in seriatum and transfer it to either an idle module, or to the module designed to execute the instruction on the specified class of operand.
Since the modules operate in parallel, they may operate simultaneously, within the constraint that normally one instruction cannot be executed until a previous instruction has been executed. While the time required to perform a single operation is about the same as in the prior hardware approach, the parallel nature of the modules significantly reduces the time to execute a program contained in the special instructions, as a free central processor unit module may be used to process interrupts. However, as each module must be capable of operating independently, circuit redundancy is necessary. Each module usually performs only one function, and is not readily converted into other functions.
In a fourth arrangement, used on conjunction with certain PDP-11 data processing systems, a separate module, termed a "floating point accelerator", processes instructions in conjunction with floating point operands. The instruction indicates whether the operand is floating point or integer, and if the instruction indicates that the operand is floating point, the central processor unit passes the instruction to the floating point accelerator. The floating point accelerator then decodes the instruction, and requests the central processing unit to retrieve operands from the memory unit for memory, and to store the processed data in the memory. While this approach allows the central processing unit the freedom to process such things as interrupts while the floating point accelerator is in the process of executing the floating point instruction, the required interaction between the central processing unit and the floating point accelerator unnecessarily complicates both units.
It is therefore an object of this invention to provide a new and improved floating point accelerator.
It is yet another object of this invention to provide a new interconnection arrangement between the floating point accelerator and the central processing unit.